Phase locked loop frequency synthesis is a well known technique for generating one of many related signals from a variable-frequency voltage-controlled-oscillator (VCO). In a single loop PLL, an output signal from the VCO is coupled to a programmable frequency divider. The programmable frequency divider divides by a selected integer number, providing a frequency divided signal to a phase detector. The phase detector compares the frequency divided signal to a reference signal from another fixed frequency oscillator (typically a relatively stable crystal oscillator). Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, via a low-pass filter, and applied to the VCO. The phase difference signal causes the output signal from the VCO to change in frequency so as to minimise the phase difference between the frequency divided signal and the reference signal. Clearly, by varying the integer by which the signal from the VCO is divided, the signal from the VCO will change correspondingly.
Since the frequency divider can only divide by integers, the earliest frequency synthesisers of this nature were only used to generate step-wise variations in the output frequency (e.g. to generate separate channel frequencies to be further modulated by a conventional mixer to generate the ultimately desired modulated rf signals). In this case an increase in the dividing integer of 1 would correspond to an increase in the output signal from the VCO of one channel spacing, the channel spacing being equal therefore to the frequency of the reference signal from the fixed frequency oscillator.
Fractional-N synthesisers have since been developed which effectively divide the output signal from the VCO by a non-integer. This is done using a similar principle to that involved in Sigma-Delta Digital-to-Analogue conversion. By rapidly varying the integer used for dividing the output signal from the VCO and then low pass filtering the phase difference signal to generate an average phase difference signal, the VCO can be made to generate a signal corresponding to a non-integer multiple of the fixed frequency reference signal.
This process can then be carried a step further to produce direct modulation of the rf carrier signal by varying the non-integer multiple of the fixed frequency reference signal to produce frequency or phase modulation, provided the rate of changing the instantaneous integer dividing value (or the sampling frequency) is higher than the highest important frequency of the modulating signal. This is easily achievable with modern systems. Such a direct modulation system is generally well known in the art and is for example described in U.S. Pat. No. 5,166,642.
The principal problem with such systems is that a large amount of noise is generated (this noise may be thought of as quantisation noise). The noise has a substantially flat frequency spectrum, on either side of the central frequency of the channel up to .+-.(sampling frequency)/2. The PLL arrangement as a whole acts as a band pass filter which reduces the effect of noise whose frequency is beyond the corner frequencies of the PLL arrangement. The frequency response of the PLL arrangement is not ideal but is nonetheless of a reasonably high order. Thus arrangements have been devised which shape the noise signal in terms of its frequency spectrum to shift the majority of the noise to frequencies beyond the corner frequencies of the PLL arrangement. The above mentioned U.S. Pat. No. 5,166,642 is an example of such an arrangement using a multiple accumulator approach to provide a suitable noise transfer function.
Such arrangements have significantly reduced the amount of noise generated by fractional-N synthesisers. However, with increasing signal-to-noise ratio requirements in modem telephonic environments, there remains a need to further reduce the noise generated by fractional-N synthesisers.
Also, two key parameters are to be considered in Direct Modulation, the peak phase error and the rms phase error of the phase modulation. For a given modulation bandwidth, the peak phase error is mainly influenced by the PLL frequency response and bandwidth which introduce a distortion on the modulation signal. To reduce this peak error, there is a need to increase the PLL bandwidth versus the modulation bandwidth, however, for higher PLL bandwidth and a given noise density, the overall noise is increased which then increases the rms phase error. Thus there is a tradeoff between PLL bandwidth and rms phase error. It would be desirable to reduce the overall rms phase error for a higher PLL bandwidth.